ESD protection is one of the many challenges electronics developers face in their work. Many materials and objects can accumulate electrostatic charges. With no proper protection, a single touch can lead to catastrophic failures, as the voltage of ESD events can reach thousands of volts.
Thus, the quality of ESD protection defines the reliability of a device and its commercial success, which is crucial for businesses dealing with electrical products.
The Nature of ESD
An electrostatic discharge (ESD) is a momentary electric current flow between two electrically charged materials or objects which is caused by contact, an electrical short, or dielectric breakdown.
Triboelectric charging or electrostatic induction can lead to the accumulation of an electrostatic charge on the surface of different objects, including the human body. If such an object happens to be near an electrical device (another electrically charged object), the voltage difference causes an electrostatic discharge.
Fig 1. A picture showing an electrostatic discharge between two electrically charged objects.
What seems like a harmless everyday event can be deadly to sensitive electronic components. By walking over a carpet, a person can accumulate up to 35,000V on his shoes. For comparison, even 10V can be destructive for sensitive integrated circuits.
According to EOS/ESD Association, inc., ESD failures can cost manufacturers from several cents to several hundred dollars per product. It may seem not much on a small scale. But in mass production, the absence of proper ESD protection can make a whole batch defective.
That’s why it’s crucial to protect electrical devices from possible ESD events.
The Difference between ESD and EOS events
EOS stands for electrical overstress. This term is often used as a synonym for ESD, which is incorrect. Electrical overcharge refers to any exposure of an electrical device or its components to a current or voltage that exceeds the device’s maximum ratings. The sources of an EOS event can be different, while the source of an ESD event is always electrostatic in nature. In this regard, one can consider ESD as a subset of EOS.
These two phenomena have other differences as well.
ESD events reach extremely high voltages (thousands of volts) and moderate peak currents. Their duration is very short (nanoseconds).
EOS events reach much lower voltages (hundreds of volts) but higher peak currents. Their duration is longer (from milliseconds to seconds).
Fig 2. Two graphs showing the difference between an EOS and an ESD event.
ESD Damage Types
The damage unprotected devices can suffer from an ESD event can be divided into four types.
- Soft failure
In a best-case scenario, a device suffers no physical damage. However, the ESD event causes malfunctions, and the device may stop working. Rebooting the system is usually enough to correct such failures.
- Data loss
In this case, an ESD event causes data corruption without inflicting physical damage. The result varies from data loss to software or firmware corruption.
- Catastrophic failure
In this case, an electrostatic charge melts metal, breakdowns junctions or insulating oxide layers. As a result, the device suffers physical damage and stops working completely.
Fig 3. ESD damage on an integrated circuit. Image source: https://nepp.nasa.gov/index.cfm/6095
4. Latent defects
Physical damage caused by an ESD event doesn’t always disrupt the work of an integrated circuit. Sometimes, the damage is not critical, and the device continues working (sometimes, with a certain performance drop).
Nevertheless, latent defects lead to degradation of the IC and will sooner or later cause a catastrophic failure.
ESD Performance of Integrated Circuits
Depending on different circumstances, an electrostatic discharge event exhibits different voltage and charge levels and different discharge characteristics. Integrated circuits are commonly rated for ESD performance by using the following methods:
- Human Body Model (HBM): simulates a charged human body discharging through the equipment under test to ground.
- Machine Model (MM): simulates a manufacturing machine becoming charged and discharging through the EUT to ground.
- Charged Device Model (CDM): simulates a charged integrated circuit discharging to a grounded metal surface.
This classification was designed for manufacturing environments. It rates a device’s ability to survive electrostatic discharge events that happen during the manufacturing process. However, when designing hardware, one has to make it suitable for real-life use.
How a device behaves in the real world is commonly estimated with the IEC 61000-4-2 standard. It describes test conditions that a device must withstand to comply with a certain ESD immunity level. The device is subjected to direct contact discharge or indirect (through air) discharge where direct contact is impossible.
IEC 61000-4-2 defines four standard ESD circuit protection levels:
| Contact Discharge | Air Discharge | ||
| Level | Test Voltage | Level | Test Voltage |
| 1 | 2 kV | 1 | 2 kV |
| 2 | 4 kV | 2 | 4 kV |
| 3 | 6 kV | 3 | 8 kV |
| 4 | 8 kV | 4 | 15 kV |
ESD Protection Methods
Although ESD and EOS are similar phenomena, engineers use different approaches to the matter of protecting devices from them.
Electrical overstress is an event that should not occur under normal operating conditions. Most measures aimed at protecting an IC from EOS events include designing the device with a higher Absolute Maximum Rating, i.e. the maximum overvoltage/overcurrent that the device can withstand. Nevertheless, using overvoltage protection devices and current limiters is also an option.
As for ESD events, one can use the following protection methods.
ESD Protection at the Development/Manufacturing Phase
The first place where a device can suffer ESD damage is the manufacturing line or the workshop (in the case of an electronics design studio). Often, poor antistatic protection used by a manufacturer leads to producing low-reliability equipment. It happens because, at this phase, devices suffer ESD events that cause latent defects which manifest themselves much later.
To avoid such consequences, manufacturers and electronics designers must establish an ESD-Protected Area (EPA). The idea of such an area is to keep the potentials on all surfaces at the same level by linking all objects and personnel to ground.
The simplest way to build an EPA is to equip the working area with an antistatic mat, grounding plug, ground cable, ESD loop, and ESD wrist strap. These are the basic elements of an EPA.
Fig 4. Basic elements of an ESD-Protected Area: an antistatic mat, ESD wrist strap, ESD loop, grounding plug, and ground cable.
For a more complicated ESD-Protected Area, one needs to use additional equipment – for example, ESD test equipment that can measure the ESD level for particular surfaces. It’s also a good idea to use ionizers that generate positive and negative ions around the surfaces of sensitive devices and components. Ionizers remove airborne particles as well, as they can cause static charge build-up due to friction.
For storage and transportation, engineers use antistatic bags and ESD packaging boxes. And finally, there’s a large selection of other pieces of equipment: antistatic gloves, shoes, ESD-safe tools, ESD tape, etc.
These measures will protect a device during development or manufacturing. But it also needs protection from ESD events that can occur during operation. And this is how this problem can be solved.
Overvoltage Protection Devices
Another way to protect an integrated circuit from electrostatic discharge events is to mount overvoltage protection devices between external connectors (possible ESD sources) and the IC. There are many types of such devices: Zener diodes, ESD suppressors, varistors, etc. Electronics designers often use transient voltage suppressor (TVS) diodes.
In a typical protection scheme, a TVS is mounted in parallel with the Protected IC between the circuit and the ESD Source. The resistance of the TVS is too high under normal operating conditions, which doesn’t allow the current to flow through it. However, once the voltage exceeds the avalanche breakdown voltage (during an ESD event), the TVS’ resistance drops.
Since the resistance of the TVS becomes lower than that of the Protected Line, it shunts the ESD current to ground, not letting it damage the Protected IC.
Fig 5. A typical scheme of a TVS diode array used for ESD protection.
The scheme below shows a TVS diode placed next to a battery connector. The connector can serve as an ESD Source. When the user replaces the battery, his body or clothes can transfer a static charge through the connector to the IC. If it happens, the NSPU3051N2T5G unidirectional ESD and surge protection device (TVS1) will shunt the excess energy to ground.
Fig 6. Using a TVS diode to protect a sensitive circuit from possible ESD at the battery connector.
This is another example of using a TVS diode – this time, it protects the IC from possible ESD coming through a USB port. The capacitors mounted before the TVS suppress low-frequency EMI from the USB and play no role in electrostatic discharge protection.
Fig 7. A TVS diode placed between a USB port and a sensitive circuit for ESD protection.
In the scheme below, the role of ESD Source is played by an ECG electrodes connector (J2) on a medical device. Since the electrodes are attached to the human body directly, this connector is especially vulnerable to potential electrostatic discharges. Hence the TVS diode between the IC and the connector.
Fig 8. A TVS diode placed between an ECG electrode connector and a sensitive circuit for ESD protection.
It is worth noting that the output pin 1 of the operational amplifier (U6) here has a very low resistance. So, it can work as another TVS diode and receive portions of ESD current. That’s why the R15 resistor was used here: it works as a second defense line.
The following application shows a PBX communications device for preventing phone frauds developed for senior citizens. In this case, engineers protected the IC from possible ESD coming from the telephone line. What’s interesting here is that the team used a TISP4350 overvoltage protector (SP1). This series was designed specifically for overvoltages on telecom lines.
Fig 9. A TISP4 overvoltage protector placed between a telephone line connector and a sensitive circuit for ESD protection.
Proper PCB Layout for ESD Protection
Along with mounting ESD protection devices, engineers can enhance a device’s ESD immunity with proper PCB layout. There are several design techniques for that.
- Optimizing impedances around the TVS
All PCB components and traces have parasitic inductances that negatively affect a circuit’s ESD immunity. In a typical protection scheme, there are four of them indicated as L1-4 in the picture below.
Fig 10. Parasitic inductances around a TVS diode array that affect the layout’s ESD protection capabilities.
The aim of a PCB designer is to make sure the L4 is much larger than other inductances, which will force ESD current to ground through the TVS.
In the following picture, you can see a USBLC6-4SC6 ESD suppressor (U2) placed between a USB port and an FT231X UART (U1).
Fig 11. A part of a PCB with an ESD suppressor placed between a USB port and the FT231X UART.
The ESD suppressor here is placed closer to the USB port (ESD Source), which makes L1 lower than L4. Additionally, the suppressor is mounted directly on the path from the ESD Source to U1, which minimizes L2.
- Limiting EMI from electrostatic discharge
As a fast transient, ESD can cause electromagnetic interference. The rapidly changing electric field can couple onto the circuits nearby and cause undesired voltages on unintended circuits. The path from the ESD Source to the TVS is the main source of EMI. That’s why designers should avoid placing unprotected circuits in this area.
One can also limit EMI by using straight and short traces, as corners tend to emit EMI. Whenever it is not possible, 45° angles can be used instead, which you can see in the picture above.
- Using VIAs properly
VIAs function just like traces between the TVS and other elements on a multilayer PCB. That’s why designers should not place the ESD Source and the Protected IC on the same layer, with the TVS located on a different layer. The picture below demonstrates the wrong way of using VIAs for ESD protection.
Fig 12. A scheme showing how not to use VIA’s for ESD protection.
In this case, the ESD current will branch between the TVS and the IC. To avoid it, developers should not place the ESD Source and the Protected IC on different layers:
Fig 13. A scheme showing the best way to use VIAs for ESD protection.
For the PCB with a USBLC6-4SC6 ESD suppressor, the designers used a similar layout, except the scheme has two ESD Sources. This layout forces the ESD current to the TVS protection pin before letting it flow to the IC.
Fig 14. A scheme showing a VIA properly used to protect a circuit from two ESD sources going through two different PCB layers.
Conclusion
Electrostatic discharge events are quite common in real-life situations. So, a device should be properly protected to function properly. Often, because of poor ESD protection, certain manufacturers are known for selling poor-quality equipment and devices. Neglecting this issue can lead to many problems, including reputational and financial loss.
There are three ways to protect a device from electrostatic discharges: by building ESD-Protected Area for the development/manufacturing phase; as well as by mounting overvoltage protection devices and using proper PCB layout for real-life situations.
By combining these groups of methods, Integra Sources and other electronics designer firms enhance a device’s ESD protection level. This, in turn, makes the device more reliable and positively affects the manufacturer’s reputation.
